1. Field of the Invention
The present invention relates to a microprocessor capable of realizing low power consumption in various information appliances (portable, sensor node, etc.), and more particularly, to a microprocessor architecture based on an event-processing instruction set provided in an instruction set architecture (ISA) that is able to operate with low power consumption as a core element of various information appliances, an event-processing method using the same.
2. Description of the Related Art
A microprocessor is one of the core components of information appliances that have been used in the field of various applications. Information appliances have increasingly become miniaturization, high-performance and low-power in recent years, and there has been an increasing demand for various techniques and technologies for minimizing power consumption due to the limits on the small portable information appliances and their battery technologies. Among them, a microprocessor has been designed using various low-power techniques since the microprocessor may be used as a core component for information process.
In the case of the conventional low-power techniques, general microprocessors have been used to reduce power consumption by decreasing an externally applied power supply voltage or reducing an operating clock rate to operate the microprocessors at low power (Dynamic Voltage Frequency Scaling: DVFS), and they have also been used to further reduce power consumption by interrupting clocks or power sources to blocks that are not necessary to operate any more.
However, the above-mentioned methods requires the time and complicated controls for the changes in the power supply voltage or the operating clock rate, also have limits in reducing the power consumption since the minimum power supply voltage or clock should be used for a period when the microprocessors waits to process predetermined internal or external events although the power supply voltage is decreased and the clock rate is reduced.
Also, a global clock used in the synchronous circuit and system designs is provided in all memory devices in the system, and therefore the dynamic power consumption is always caused due to the increased capacitive load by the use of clock wires and the signal transition by the supply of the clock signal, which accounts for some of the entire power consumption.
Therefore, the above-mentioned method has a limit in reducing the power consumption when the method is used in the synchronous microprocessors although the method is applicable through the various techniques and complicated controls.
As an alternative, EP0931287 B1 (Title: “Asynchronous Data Processing Apparatus”) filed by ARM (England) and Manchester University discloses a microprocessor that operates without the use of global clocks through the application of the asynchronous circuit and system design methodologies so as to solve the low-power-associated problem as described above.
For the European patent, the microprocessor may operate at low power by preventing the increased wires of global clocks and thus the increase in capacitive load since the global clocks are not used in the microprocessor, and also cutting off the power consumption according to the clock transition caused even when the microprocessor does not operate.
Also, the microprocessor may be realized at low power by halting some circuits of the microprocessor if the operation of the circuits is not necessary when the operation of the program in the microprocessor is completed through the instruction “HALT” for halting operation of a microprocessor in an instruction set architecture (ISA) of the microprocessor.
However, for the above-mentioned method, the microprocessor may operate again by receiving external hardware interrupts, analyzing the received interrupts, and processing an operation based on the analysis of the interrupts using a software, and therefore it is difficult to define the kinds and characteristics of the external interrupts. Also when external interrupts are generated, the microprocessor should analyze the external interrupts using its software, and take its operation according to the analyzed external interrupts.
Therefore, the conventional microprocessors have a problem that, although unnecessary interrupts are generated in the operation of the microprocessors, the microprocessors should be certainly re-run to confirm the generation of the interrupts and take their operation.
As another alternative, US Patent No. 2006/0075210 A1 (Title: “Sensor-Network Processors Using Event-Driven Architecture”) filed by Rajit Manohar from Cornell University (US) proposes a configuration of a microprocessor capable of its preventing power consumption by the unnecessary operation of a microprocessor when the microprocessor is in waiting state to process internal or external events after the operation of the microprocessor is completed normally.
For the configuration and method proposed in the US patent, when necessary operations of the microprocessor are completed, the microprocessor executes the instruction “DONE” instruction (identical to the instruction “HALT” in the European patent) to halt the operation of the microprocessor, generates an event token through a timer and a message coprocessor, both of which function to process unnecessary events, when the unnecessary events are generated in the microprocessor, and re-execute its corresponding operation when there is an generated token.
The method proposed in the US patent may be used to effectively reduce the power consumption in the microprocessor when the asynchronous circuit and system design methodologies apply to the microprocessor, but has a problem that various coprocessors and queues should be used to generate an event token that is necessary to re-operate the microprocessor when the operation of the microprocessor comes to a halt.
In the case of the above-mentioned methods, the microprocessor should be necessarily re-operated to confirm the generation of interrupts and takes its operation even when the generated interrupts are irrelevant to the execution of programs in the microprocessor, which leads to the additional power consumption. Also, the size and volume of a circuit may be increased since various coprocessors and queues should be used to generate an event token that is necessary to re-operate the microprocessor when the operation of the microprocessor comes to a halt.